Novel CMOS device

ABSTRACT

A method for improving the mobility of holes and electrons within a structure comprising the following steps. A structure having at least an adjacent NMOS device and PMOS device is provided. A first stress layer is formed over the PMOS device and a second stress layer is formed over the NMOS device whereby the mobility of holes and electrons within the structure is improved. A semiconductor device comprising: at least one NMOS device; at least one PMOS device adjacent the at least one NMOS device; a first stress layer overlying the at least one PMOS device with the first stress layer having a first stress characteristic; and a second stress layer overlying the at least one NMOS device with the second stress layer having a second stress characteristic.

FIELD OF THE INVENTION

[0001] The present invention relates generally to semiconductorfabrication and more specifically to metal-oxide semiconductor (MOS)devices/complimentary MOS (CMOS) devices and methods of forming thesame.

BACKGROUND OF THE INVENTION

[0002] Mechanical stress control in the channel regions of metal-oxidesemiconductor field-effect transistors (MOSFETs) enables overcoming thelimitations incurred in the scaling down of devices.

[0003] U.S. Pat. No. 6,284,610 B1 to Cha et al. describes a poly layerto reduce stress.

[0004] U.S. Pat. No. 6,281,532 B1 to Doyle et al. describes processes tochange the localized stress.

[0005] U.S. Pat. No. 5,562,770 to Chen et al. describes a process forglobal stress modification by forming layers or removing layers fromover a substrate.

[0006] U.S. Pat. No. 5,834,363 to Masanori describes a method for globalstress modification by forming layers from over a substrate.

[0007] The J. Welser et al. Strain Dependence of the PerformanceEnhancement in Strained-Si n-MOSFETs, IEDM Tech. Dig., pp. 373- 376,1994 article discloses measurements of the strain dependence of theelectron mobility enhancements in n-MOSFETs employing tensilely-strainedSi channels.

[0008] The K. Rim et al. Strained Si NMOSFET's for High Performance CMOSTechnology, VLSI Tech., pp. 59 and 60, 2001 article describesperformance enhancements in strained Si NMOSFET's at L_(eff)<70 nm.

[0009] The F. Ootsuka et al. A Highly Dense, High-Performance 130 nmnode CMOS Technology for Large Scale System-on-a-Chip Applications, IEDMTech. Dig., pp. 575-578, 2000 article describes a 130 nm node CMOStechnology with a self-aligned contact system.

[0010] The Shinya Ito et al. Mechanical Stress Effect of Etch-StopNitride and its Impact on Deep Submicron Transistor Design, IEDM Tech,Dig.; pp. 247-250, 2000 article describes process-induced mechanicalstress affecting the performance of short-channel CMOSFET's.

[0011] The A. Shimizu et al. Local Mechanical-Stress Control (LMC): ANew Technique for CMOS-Performance Enhancement, IEDM Tech. Dig., pp.433-436, 2001 article describes a “local mechanical-stress control”(LMC) technique used to enhance the CMOS current drivability.

SUMMARY OF THE INVENTION

[0012] Accordingly, it is an object of one or more embodiments of thepresent invention to provide a MOS/CMOS device having different stresseson at least two different areas, and methods of fabricating the same.

[0013] Other objects will appear hereinafter.

[0014] It has now been discovered that the above and other objects ofthe present invention may be accomplished in the following manner.Specifically, a structure having at least an adjacent NMOS device andPMOS device is provided. A first stress layer is formed over the PMOSdevice and a second stress layer is formed over the NMOS device wherebythe mobility of holes and electrons within the structure is improved. Asemiconductor device comprising: at least one NMOS device; at least onePMOS device adjacent the at least one NMOS device; a first stress layeroverlying the at least one PMOS device with the first stress layerhaving a first stress characteristic; and a second stress layeroverlying the at least one NMOS device with the second stress layerhaving a second stress characteristic.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present invention will be more clearly understood from thefollowing description taken in conjunction with the accompanyingdrawings in which like reference numerals designate similar orcorresponding elements, regions and portions and in which:

[0016] FIGS. 1 to 5 schematically illustrate a preferred embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0017] Information Known to the Inventors—Not to be Considered Prior Art

[0018] The following information is known to the inventors and is not tobe necessarily considered prior art for the purposes of this invention.

[0019] Changing the Si lattice spacing to a value other than theequilibrium value by using mechanical stress can increase the mobilityof holes and electrons. This has been demonstrated in a strained-silicon(Si) MOSFET which applied high biaxial tensile stress to the channel ofMOSFETs. However, the fabrication of strained-Si MOSFETs involvescomplicated processes such as forming a relaxed SiGe buffer layer. Arecent study has shown that mechanical stress from a contact etch stopsilicon nitride (SiN) layer affects the drive current.

[0020] Initial Structure—FIG. 1 As shown in FIG. 1, the preferredstructure of the present embodiment includes a structure 10 thatpreferably includes (1) at least one NMOS region 12 having at least oneNMOS (N-type MOS) device 16 formed therein and (2) at least one PMOSregion 14 having at least one PMOS (P-type MOS) device 18 formedtherein.

[0021] An isolation device 11 may be formed within structure 10 betweenadjacent NMOS/PMOS devices 16, 18. Structure 10 may be a siliconsubstrate or a silicon-germanium substrate, for example, and isolationdevice 11 may be, for example, a shallow trench isolation (STI) device.

[0022] The NMOS devices(s) 16 comprise a respective electrode 20 andsidewall spacers 22, source/drain (S/D) implants (not shown) and a gateoxide layer 21. The PMOS devices(s) 18 comprise a respective electrode30 and sidewall spacers 32, source/drain (S/D) implants (not shown) anda gate oxide layer 31. The respective gate oxide layers 21, 31 each havea thickness of preferably from about 6 to 100 Å and more preferably lessthan about 17 Å.

[0023] An NMOS device channel and a PMOS device channel may be formed(not shown). The respective device channels each have a design width ofpreferably from about 0.05 to 10.0 μm, more preferably less than about10.0 μm and most preferably less than about 0.5 μm.

[0024] The operation voltage design is preferably from about 0.6 to 3.3volts (V) and is more preferably less than about 1.2 V.

[0025] Structure 10 is preferably a silicon substrate or a germaniumsubstrate, is more preferably a silicon substrate and is understood topossibly include a semiconductor wafer or substrate.

[0026] A first stress layer 40 is formed over structure 10, NMOSdevices(s) 16 and PMOS device(s) 18 to a thickness of preferably fromabout 200 to 700 Å. First stress layer 40 may be either a tensile-stresslayer or a compression-stress layer as described below.

[0027] An etch stop layer 42 is formed over the first stress layer 40 toa thickness of preferably from about 200 to 700 Å and more preferablyfrom about 250 to 500 Å. Etch stop layer 42 is preferably comprised ofoxide, silicon oxide (SiO₂) or SiON and is more preferably comprised ofoxide or silicon oxide.

[0028] A first patterning layer 46 is formed at least over either theNMOS device 16 and adjacent thereto or, as shown in FIG. 1, the PMOSdevice 18 and adjacent thereto, to permit patterning of the etch stoplayer42 and the first stress layer 40. First patterning layer 46 ispreferably comprised of photoresist, or a hardmask and more preferablyphotoresist as shown in FIGS. 1 and 2. Etch stop layer 42 may also bepatterned by selective etching without using a first patterning layer46.

[0029] Patterning of the Etch Stop Layer 42 and the First Stress layer40—FIG. 2

[0030] As shown in FIG. 2, preferably using first patterning layer 46 asa mask, the etch stop layer 42 and the first stress layer 40 arepatterned to leave a patterned etch stop layer 42′ and a patterned firststress layer 40′ each at least overlying the PMOS device 18 and adjacentthereto within PMOS area 14, leaving the NMOS device 16 within NMOS area12 exposed.

[0031] As one skilled in the art would understand now or hereafter, thefirst patterning layer 46 may not necessarily be needed to pattern theetch stop layer 42 and the first stress layer 40 as long as the etchstop layer 42 and the first stress layer 40 are patterned/etched asshown in FIG. 2.

[0032] Formation of Second Stress layer 50—FIG. 3

[0033] As shown in FIG. 3, the first patterning layer 46 (if used) isremoved and the structure is cleaned as necessary.

[0034] A second stress layer 50 is formed over structure 10, NMOS device16 and over patterned etch stop layer 42′ that overlies at least PMOSdevice 18 and adjacent thereto to a thickness of preferably from about200 to 700 Å. Second stress layer 50 is (1) a tensile-stress layer ifthe patterned first stress layer 40′ is comprised of a tensile-stresslayer and is a (2) a tensile-stress layer is the patterned first stresslayer 40′ is comprised of a compression-stress layer.

[0035] As shown in FIG. 3, a second patterning layer 48 is formed atleast over the NMOS device 16 (if the first patterning layer 46 wasformed over the PMOS device 18) and adjacent thereto to permitpatterning of the second stress layer 50. Second patterning layer 48 ispreferably comprised of photoresist or a hardmask and more preferablyphotoresist as shown in FIGS. 3 and 4. Second stress layer 50 may alsobe patterned by selective etching without using a first patterning layer48.

[0036] Patterning of the Second Stress Layer 50—FIG. 4

[0037] As shown in FIG. 4, preferably using second patterning layer 48as a mask: (1) the second stress layer 50 is patterned to leave apatterned second stress layer 50′ at least overlying the NMOS device 16and adjacent thereto within NMOS area 12; and (2) the patterned etchstop layer 42′ is etched and removed leaving the patterned first stresslayer 40′ overlying at least the PMOS device 18 and adjacent theretowithin PMOS area 14 exposed.

[0038] As one skilled in the art would understand now or hereafter, thesecond patterning layer 48 may not necessarily be needed to pattern thesecond stress layer 50 et al. as long as the second stress layer 50 etal. are patterned/etched as shown in FIG. 4.

[0039] Removal of the Second Patterning Layer 48—FIG. 5

[0040] As shown in FIG. 5, the second patterning layer 48 (if used) isremoved and the structure is cleaned as necessary.

[0041] Formation of Tensile-Stress Layers and Compression-Stress Layers

[0042] As noted above, the first stress layer 40 may be either atensile-stress layer or a compression-stress layer while the secondstress layer 50 is a tensile-stress layer. That is, if the first stresslayer 40 is a tensile-stress layer then the second stress layer 50 is atensile-stress layer, and if the first stress layer 40 is acompression-stress layer then the second stress layer 50 is atensile-stress layer as illustrated by the following table: Case 1 Case2 First Stress layer 40′ tensile-stress compression-stress Second Stresslayer 50′ tensile-stress tensile-stress

[0043] The tensile-stress layer, be it first stress layer 40 or secondstress layer 50, is preferably comprised of silicon nitride (Si₃N₄ orjust SiN), silicon oxynitride (SiON), oxide or Si-rich nitride, is morepreferably SiN or SiON and is most preferably SiON and has a thicknessof preferably from about 200 to 1000 Å and more preferably from about250 to 500 Å. The tensile-stress layer is preferably deposited by rapidthermal chemical vapor deposition (RTCVD) under the followingconditions:

[0044] temperature: preferably from about 350 to 800° C. and morepreferably from about 400 to 700° C.;

[0045] time: preferably from about 10 to 2000 seconds and morepreferably from about 20 to 120 seconds;

[0046] NH₃:SiH₄ gas ratio: preferably from about 50:1 to 400:1 and morepreferably less than about 700:1; or di-saline:NH₃ gas ratio: preferablyfrom about 1:40 to 1:500 and more preferably less than about 1:1; and

[0047] deposition pressure: preferably from about 10 to 400 Torr andmore preferably less than about 300 Torr.

[0048] The compression-stress layer, which may be first stress layer 40,is preferably comprised of silicon nitride (Si₃N₄ or just SiN), siliconoxynitride (SiON), oxide or Si-rich nitride, is more preferably SiN orSiON and is most preferably SiON and has a thickness of preferably fromabout 200 to 1000 Å and more preferably from about 250 to 500 Å. Thecompression-stress layer is preferably deposited by plasma enhancedchemical vapor deposition (PECVD) under the following conditions:

[0049] temperature: preferably from about 300 to 600° C. and morepreferably less than about 600° C.;

[0050] time: preferably from about 10 to 500 seconds and more preferablyfrom about 20 to 120 seconds;

[0051] NH₃:SiH₄ gas ratio: preferably from about 4:1 to 10:1 and morepreferably less than about 8:1; or di-saline:NH₃ gas ratio: preferablyfrom about 1 :4 to 1:10 and more preferably less than about 1:1;

[0052] deposition pressure: preferably from about 1.0 to 1.5 Torr andmore preferably less than about 1.5 Torr; and

[0053] total power: preferably from about 1000 to 2000 watts (W) andmore preferably greater than about 1000 W.

[0054] The different stresses achieved by using either a firsttensile-stress layer 40′/second compression-stress layer 50′ combinationor a first compression-stress layer 40′/second tensile-stress layer 50′combination in accordance with the teachings of the present inventionincreases the mobility of holes and electrons.

[0055] Advantages of the Present Invention

[0056] The advantages of one or more embodiments of the presentinvention include:

[0057] 1. using a specific tensile film to improve N, PMOS; and

[0058] 3. provide a method to attain PMOS on compressive stress and NMODon tensile stress to improve N, PMOS device performance.

[0059] While particular embodiments of the present invention have beenillustrated and described, it is not intended to limit the invention,except as defined by the following claims.

We claim:
 1. A method for improving the mobility of holes and electronswithin a structure, comprising the steps of: providing a structurehaving at least an adjacent NMOS device and PMOS device; forming a firststress layer over the PMOS device; and forming a second stress layerover the NMOS device; whereby the mobility of holes and electrons withinthe structure is improved.
 2. The method of claim 1, wherein thestructure is a silicon substrate or a silicon-germanium substrate. 3.The method of claim 1, wherein the structure is a silicon substrate. 4.The method of claim 1, wherein the first stress layer is atensile-stress layer and the second stress layer is a tensile-stresslayer.
 5. The method of claim 1, wherein the first stress layer is acompression-stress layer and the second stress layer is a tensile-stresslayer.
 6. The method of claim 1, wherein the first stress layer and thesecond stress layer are each comprised of Si-rich nitride, SiON or SiN.7. The method of claim 1, wherein: the first stress layer is atensile-stress layer and the second stress layer is a tensile-stresslayer; or the first stress layer is a compression-stress layer and thesecond stress layer is a tensile-stress layer; and the tensile-stresslayer is deposited by a rapid thermal CVD process; and thecompression-stress layer is deposited by a PECVD process.
 8. The methodof claim 1, wherein: the first stress layer is a tensile-stress layerand the second stress layer is a tensile-stress layer; or the firststress layer is a compression-stress layer and the second stress layeris a tensile-stress layer; and the tensile-stress layer is deposited bya rapid thermal CVD process under the following conditions: temperature:from about 350 to 800° C.; time: from about 10 to 2000 seconds; NH₃:SiH₄gas ratio: from about 50:1 to 400:1; or di-silane:NH₃ gas ratio: fromabout 1:40 to 1:500; and deposition pressure: from about 10 to 400 Torr;and the compression-stress layer is deposited by a PECVD process underthe following conditions: temperature: from about 300 to 600° C.; time:from about 10 to 500 seconds; NH₃:SiH₄ gas ratio: from about 4:1 to10:1; or di-silane:NH₃ gas ratio: from about 1:4 to 1:10; depositionpressure: from about 1.0 to 1.5 Torr; and total power: from about 1000to 2000 watts.
 9. The method of claim 1, wherein the first and secondstress layers each have a thickness of from about 200 to 700 Å.
 10. Themethod of claim 1, wherein: the first stress layer is acompression-stress layer and the second stress layer is a tensile-stresslayer; or the first stress layer is a tensile-stress layer and thesecond stress layer is a tensile-stress layer; the tensile-stress layeris deposited by a rapid thermal CVD process under the followingconditions: temperature: from about 350 to 800° C.; time: from about 10to 2000 seconds; NH₃:SiH₄ gas ratio: from about 50:1 to 400:1; ordi-silane:NH₃ gas ratio: from about 1:40 to 1:500; and depositionpressure: from about 10 to 400 Torr; and the compression-stress layer isdeposited by a PECVD process under the following conditions:temperature: from about 300 to 600° C.; time: from about 10 to 500seconds; NH₃:SiH₄ gas ratio: from about 4:1 to 10:1 ; or di-silane:NH₃gas ratio: from about 1:4 to 1:10; deposition pressure: from about 1.0to 1.5 Torr; and total power: from about 1000 to 2000 watts.
 11. Themethod of claim 1, wherein the NMOS device and the PMOS device eachinclude a gate oxide layer having a thickness of less than about 15 Å.12. The method of claim 1, wherein the NMOS device and the PMOS deviceeach have a device channel having a design width of less than about 0.5μm.
 13. The method of claim 1, wherein the operation voltage design ofthe NMOS device and the PMOS device is less than about 1.2 volts.
 14. Asemiconductor device comprising: at least one NMOS device; at least onePMOS device adjacent the at least one NMOS device; a first stress layeroverlying the at least one PMOS device; the first stress layer having afirst stress characteristic; and a second stress layer overlying the atleast one NMOS device; the second stress layer having a second stresscharacteristic; whereby the first stress characteristic is tensile andthe second stress characteristic is tensile; or the first stresscharacteristic is compressive and the second stress characteristic. 15.The device of claim 14, wherein the structure is a silicon substrate ora silicon-germanium substrate.
 16. The device of claim 14, wherein thestructure is a silicon substrate.
 17. The device of claim 14, wherein:the first stress layer is a rapid thermal CVD layer and the secondstress layer is a rapid thermal CVD layer; or the first stress layer isa PECVD layer and the second stress layer is a rapid thermal CVD layer.18. The device of claim 14, wherein the first stress layer and thesecond stress layer are each comprised of SiON.
 19. The device of claim14, wherein the NMOS device and the PMOS device each further includes agate oxide layer having a thickness of less than about 17Å.
 20. Thedevice of claim 14, wherein the NMOS device and the PMOS device eachfurther includes a device channel having a design width of less thanabout 0.5 μm.
 21. The device of claim 14, wherein the semiconductordevice has an operation voltage design of less than about 1.2 volts. 22.The device of claim 14, whereby the semiconductor device has improvedmobility of holes and electrons.
 23. The device of claim 14, wherein thesemiconductor device further includes an isolation structure between theat least one NMOS device and the at least one PMOS device.
 24. Thedevice of claim 14, wherein the semiconductor device further includes anSTI structure between the at least one NMOS device and the at least onePMOS device.
 25. The device of claim 14, wherein the at least one NMOSdevice further includes sidewall spacers and the at least one PMOSdevice further includes sidewall spacers.
 26. The device of claim 14,wherein the first stress layer and the second stress layer 50′ are eachcomprised of Si-rich nitride, SiON or SiN.
 27. A semiconductor devicecomprising: at least one NMOS device; at least one PMOS device adjacentthe at least one NMOS device; a first stress layer overlying the atleast one PMOS device; the first stress layer having a first stresscharacteristic; and a second stress layer overlying the at least oneNMOS device; the second stress layer having a second stresscharacteristic; whereby: (1) the first stress characteristic is tensileand the second stress characteristic is tensile, or the first stresscharacteristic is compressive and the second stress characteristic; and(2) the first stress layer is a rapid thermal CVD layer and the secondstress layer is a rapid thermal CVD layer; or the first stress layer isa PECVD layer and the second stress layer is a rapid thermal CVD layer.28. The device of claim 27, wherein the structure is a silicon substrateor a silicon-germanium substrate.
 29. The device of claim 27, whereinthe structure is a silicon substrate.
 30. The device of claim 27,wherein the first stress layer and the second stress layer are eachcomprised of SiON.
 31. The device of claim 27, wherein the NMOS deviceand the PMOS device each further includes a gate oxide layer having athickness of less than about 17Å.
 32. The device of claim 27, whereinthe NMOS device and the PMOS device each further includes a devicechannel having a design width of less than about 0.5 μm.
 33. The deviceof claim 27, wherein the semiconductor device has an operation voltagedesign of less than about 1.2 volts.
 34. The device of claim 27, wherebythe semiconductor device has improved mobility of holes and electrons.35. The device of claim 27, wherein the semiconductor device furtherincludes an isolation structure between the at least one NMOS device andthe at least one PMOS device.
 36. The device of claim 27, wherein thesemiconductor device further includes an STI structure between the atleast one NMOS device and the at least one PMOS device.
 37. The deviceof claim 27, wherein the at least one NMOS device further includessidewall spacers and the at least one PMOS device further includessidewall spacers.
 38. The device of claim 27, wherein the first stresslayer and the second stress layer are each comprised of Si-rich nitride,SiON or SiN.
 39. A method for improving the mobility of holes andelectrons within a structure, comprising the steps of: providing astructure having at least an adjacent NMOS device and PMOS device;forming a first stress layer over the PMOS device; and forming a secondstress layer over the NMOS device; whereby the mobility of holes andelectrons within the structure is improved and wherein: the first stresslayer is a tensile-stress layer and the second stress layer is atensile-stress layer; or the first stress layer is a compression-stresslayer and the second stress layer is a tensile-stress layer.
 40. Themethod of claim 39, wherein the structure is a silicon substrate or asilicon-germanium substrate.
 41. The method of claim 39, wherein thestructure is a silicon substrate.
 42. The method of claim 39, whereinthe first stress layer and the second stress layer are each comprised ofSi-rich nitride, SiON or SiN.
 43. The method of claim 39, wherein: thetensile-stress layer is deposited by a rapid thermal CVD process; andthe compression-stress layer is deposited by a PECVD process.
 44. Themethod of claim 39, wherein: the tensile-stress layer is deposited by arapid thermal CVD process under the following conditions: temperature:from about 350 to 800° C.; time: from about 10 to 2000 seconds; NH₃:SiH₄gas ratio: from about 50:1 to 400:1; or di-silane:NH₃ gas ratio: fromabout 1:40 to 1:500; and deposition pressure: from about 10 to 400 Torr;and the compression-stress layer is deposited by a PECVD process underthe following conditions: temperature: from about 300 to 600° C.; time:from about 10 to 500 seconds; NH₃:SiH₄ gas ratio: from about 4:1 to10:1; or di-silane:NH₃ gas ratio: from about 1:4 to 1:10; depositionpressure: from about 1.0 to 1.5 Torr; and total power: from about 1000to 2000 watts.
 45. The method of claim 39, wherein the first and secondstress layers each have a thickness of from about 200 to 700 Å.
 46. Themethod of claim 39, wherein: the tensile-stress layer is deposited by arapid thermal CVD process under the following conditions: temperature:from about 350 to 800° C.; time: from about 10 to 2000 seconds; NH₃:SiH₄gas ratio: from about 50:1 to 400:1; or di-silane:NH₃ gas ratio: fromabout 1:40 to 1:500; and deposition pressure: from about 10 to 400 Torr;and the compression-stress layer is deposited by a PECVD process underthe following conditions: temperature: from about 300 to 600° C.; time:from about 10 to 500 seconds; NH₃:SiH₄ gas ratio: from about 4:1 to10:1; or di-silane:NH₃ gas ratio: from about 1:4 to 1:10; depositionpressure: from about 1.0 to 1.5 Torr; and total power: from about 1000to 2000 watts.
 47. The method of claim 39, wherein the NMOS device andthe PMOS device each include a gate oxide layer having a thickness ofless than about 15 Å.
 48. The method of claim 39, wherein the NMOSdevice and the PMOS device each have a device channel having a designwidth of less than about 0.5 μm.
 49. The method of claim 39, wherein theoperation voltage design of the NMOS device and the PMOS device is lessthan about 1.2 volts.